A 1.8V Sample-and-Hold with Reduced Flicker Noise

In this paper, CMOS Sample-and-Hold (S/H) is presented. The S/H circuit is an important component in Analog-to-digital Converter (ADC). In low frequency application, the boost clock technique is used to constitute a rail-to-rail signal voltage with low distortion. The operational amplifier works as a unity gain buffer in the S/H circuit. However, a two-stage op-amp is proposed with enhanced low flicker noise performance. Furthermore, a comparison between the folded-cascode op-amp and the two stage op-amp is presented. Noise minimization is mainly achieved through using the inter-relationship of the design parameters of the op-amp. This design is simulated in 0.18μm standard technology. A very low input noise voltage 18 nV/ Hz is realized. The power dissipation is about 55 μW at 1.8 V supply voltage, 1 MHz clock sampling.